(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and structure for providing ESD protection.
(2) Description of the Prior Art
One of the undesired side-effects of creating semiconductor devices is the accumulation of an electromagnetic charge, which can essentially occur at difficult to predict locations and which can randomly discharge. This random electrostatic discharge (referred to as ESD) is typically uncontrolled in its origin and in its occurrence and is prone to damage one or more of the elements that are part of a semiconductor device. The most likely source of the accumulation of electrostatic voltage is the frictional rubbing together of adjacent surfaces or bodies. Another source that is prone to create ESD is lightning, which can randomly distribute electrostatic voltage throughout an affected semiconductor device, thus damaging for instance thin layers of dielectric or causing junction breakdown in for instance Field Effect Transistors (FET). With increased device miniaturization it is reasonable to expect that ever smaller device features are becoming even more prone to device damage caused by ESD since ESD will have a relatively larger effect on smaller and thinner device features.
High-density semiconductor devices such as multi-chip modules and other electronic devices are typically created using unpackaged semiconductor devices. The functions of electrically contacting devices are provided by device pads on the die, which make contact with a carrier package. ESD circuits are typically provided to form an electric path from input/output pads of a die to a ground pad on the die or to a power or bias voltage path for the die. This electrical path is designed to be activated by a high voltage (such as an electrostatic discharge) that is applied to the input or output pads of the die. Most typically, ESD circuits are provided between input/output pads on an unpackaged die and the transistor gates to which the pads are electrically connected.
Conventional ESD protection circuits are frequently formed using impurity implants for the creation of the ESD device. Numerous methods are available, using N-type and P-type implants, to create ESD devices. One such method is provided by U.S. Pat. No. 5,953,601, which is for purposes of reference briefly highlighted at this time. This method is specifically provided for the technology of device feature size of 0.35 μm or less and provides for simultaneously creating FET devices and ESD protection circuits on the surface of a substrate. In forming the ESD source and drain regions, the conventional implantation species is changed from phosphorous to boron, thereby reducing the junction breakdown voltage. Ion implantation is then judiciously performed in areas that have high leakage currents and high parasitic capacitance. These ion implantations assure reduced breakdown voltages, as well as reduced leakage currents and reduced parasitic capacitances of the affected junctions. In addition, ion implantation is performed using a photoresist mask for the formation of silicidation over the contact surfaces. This avoids the problem of silicide degradation and the concomitant increase of contact resistance caused by the moving of metal ions into depletion regions of the junctions during high-energy ESD implantation.
The invention provides a method that negates the need for impurity implantation in order to create an ESD protection device. The invention teaches a special process flow and further provides for a leakage path, created by a contact etch, for the ESD protection function.
U.S. Pat. No. 5,618,740 (Huang) shows a CMOS with enhanced ESD resistance having a contact etch process.
U.S. Pat. No. 6,258,672 (Shih et al.) shows a method for an ESD device.
U.S. Pat. No. 5,891,792 (Shih et al.) and U.S. Pat. No. 5,953,601 (Shiue et al.) reveals other ESD processes.